The 2nd International Conference on Computer modelling and simulation
Come and meet HCL ERS team at the ICCMS, China and get an insight on AXI compliant DDR3 memory controllers
HCL is presenting a paper on the implementation of AXI compliant DDR3 memory controller. It discusses the overall architecture of the DDR3 controller along with the detailed design and operation of its individual sub blocks, the pipelining implemented in the design to increase the design throughput. It also discusses the advantage of DDR3 memories over DDR2 memories and the AXI protocol operation.
Hear the answer to these questions
Speaker for the Session: Nusrat Ali (Project Manager)
Session Time & Date : January 22nd – 24th, 2010