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ASIC Design

ASIC Design

Customer

A technology startup company

The Challenge

The customer required quick turn-out for an ASIC based on 0.13u TSMC Technology with 12 Million Gate Logic gates, 12Mbit Memory, 200 MHz core, multiple clock domains, 29 PLL/DLL, 8 metal Layers and a Die size of 17.5*17.5

HCL’s Solution

HCL’s ASIC engineering team, leveraging more than 1000 person years of experience and expertise in using complex tools, proven ASIC design methodology, robust verification and validation processes and a achieved First Pass Silicon Success

Value Delivered

HCL’s use of Silicon IPs helped improve time-to-market for the product

DOWNLOAD THE SUCCESS STORY

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We will treat any information you submit with us as confidential. Please read our privacy statement for additional information.