VLSI, ASIC & FPGA Design
HCL provides concept to silicon VLSI, ASIC, and FPGA engineering services to telecom and networking customers.
HCL’s concept to silicon capabilities are:
- Understanding customers' idea
- System modeling
- RTL coding
- Functional verification and simulation
- FPGA prototyping
- Synthesis and timing analysis
- Physical design
- Package, test, and assembly
- Engineering sample generation
HCL's technical competence in ASIC and FPGA design are:
- Die size - 18mmx18.4mm
- Technology - 65/45/40/32*/28* nm
- 21 embedded processors in one die
- Complexity design of up to 20Mgates
- Verification up to 25Mgates
- Clocks 8/Chip, 720 MHz
- Complexity design of up to 6Mgates
- I/O high speed - SERDES DDR2
- Speed - 8Gbps
- Clocks - 8 clock domains, 311MHz frequency
- Processors - ARM, NIOS, Power PC, Micro Blaze.
HCL’s domain strengths are in the areas of storage area networks, base station controllers, optical networks, and IPTV. The networking IPs which are currently available include SPI-3 link, Utopia L2/L3, CSIX, SPI 4.2, 10/100/1000M Ethernet MAC, MIL-1553, ARINC 429, CAN 2.0, and 10G MAC.
What We’ve Done For Others
- For a leading telecom infrastructure provider, HCL helped in the re-architecture of a key product that involved MPLS-TP integration. HCL’s team of experts executed control plane extension, fast path extension, and CLI / SNMP enhancement.