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Detecting Boundary Condition Bugs through System Verilog Functional Coverage

Detecting Boundary Condition Bugs through System Verilog Functional Coverage

Abstract
 
This document describes the necessity to identify the boundary condition bugs present in design modules; and discusses about the effective solution provided through functional coverage over code (condition) coverage in  making sure that such scenarios are identified during verification.
 
Excerpts from the Paper

Boundary conditions present in a design module are crucial check items which should be identified and listed by the module designer for the purpose of verification. The boundary conditions are not covered in code coverage; so there should be some other way to make sure that they are not missed during verification. If the boundary conditions are not verified thoroughly during the block level verification of a module then there remains a possibility of a major bug being carried over to the system level. Since through code coverage (condition coverage) it is not possible to know whether boundary conditions have been covered or not, it is necessary to use functional coverage. The following sections analyze a real boundary condition bug scenario and discuss about how code coverage was not sufficient in tracking it. The possible boundary conditions for the bug scenario are listed and the implementation  detail  of one  using  System Verilog is mentioned.

 

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