With over 25+ years in the VLSI design industry and long-term partnerships with top chip manufacturers and design foundries across the globe, HCL has well-proven capabilities in Analog, Digital and Mixed Signal designs to handle the challenges of ‘Concept to Chip’ with ever-increasing complexity of the solutions as well as advanced technology nodes.
We comprehend changing customer needs and accordingly develop and deliver innovative future-enabled solutions. We are well equipped to complement and support our customers in sustaining their current product portfolio by handling the derivative designs so that they can focus on futuristic product solutions. Our engineers have varying levels of hands-on experience in domain knowledge, latest technologies, design methodologies, modeling languages, and verification techniques used in the VLSI industry.
Our Silicon Validation Labs, ATE Tester Labs, Qual Labs help our customers get not just well-designed Silicon, but also fully qualified silicon that can be manufactured seamlessly. Our foundry and OSAT partners help customers to get a full end-to-end turnkey solution.
Technology and Domain Expertise: Extensive SoC development experience of over 200 SoCs taped out, multi-domain experience in image and video processors, wireless systems and telecommunications, storage area networks, base station controllers, optical networks, HPC, SSD, automotive engine control, body electronics, and strong IP and manufacturing ecosystem knowledge.
Design and System Engineering: Processor-based platform and sub-system design, experience in high-speed interface – DDR4, PCIe, USB, 10G Serial PHY, latest verification technology using OVM, VMM, System Verilog, and experience in left shifting the silicon life cycle using emulation based post-silicon validation.
Silicon Engineering: Experience in advanced technology nodes across all major foundries – 16nm, 14 nm, 10nm, 7 nm, proven design methodology, High-performance ARM (ARM9, ARM11, Cortex - A5, A8, A9, A7, A53, A72), Intel Xeon class, RISC-V and custom processor cores, integration of complex high-speed analog IPs.
Post Silicon Validation: Experience in developing test content and testing of SoC across Silicon bring-up, functional validation, electrical interface characterization, performance optimization, and volume Validation to take the silicon through engineering sample, quality sample, and released sample. Experience in developing ATE Test program on a variety of ATE Testers for use in wafer sort and packaged testing. Experience in development of load board and probe card for the silicon manufacturing testing. Experience in testing Silicon for reliability and qualification across various industry standards.
Standards and interfaces handled: H.264, JPEG, JPEG2000, HDMI, MIPI, CSI2, USB, Ethernet, SDIO, SATA, DDR4 / DDR3, LPDDR, HMC, HBM, NAND, PCIe Gen4, 3D XPoint, NVMe, MIPI I3C, CPRI, H.265.
Our key differentiators are our proven flow and framework for execution, silicon design complemented by platform capabilities, in-house emulation platform, in-house FPGA development, prototyping kits, high speed testing labs, and extensive experience in project/program ownership.
With the changing times HCL has established a standard framework for remote working for its engineers considering the infrastructure requirements and security consideration of customer IP requirements.
Realizing IC designs involving architecture design, system modelling, RTL coding, developing full-functional FPGA prototypes, verification, synthesis, test vector generation & minimization, simulation and back-end support.
Analog / digital / mixed signal verification, ASIC / FPGA / SoC verification, IP level verification, third party module verification across various design complexities / programming languages / methodologies and industrial verticals. Experience in all formal methodologies.
A comprehensive line of rapid FPGA based prototyping and emulating complex IC designs to develop first pass silicons. Extensive experience in Industry Standard Platforms such as Zebu, Palladium, Veloce, HAPS, COTS FPGA and Custom FPGA prototyping platforms.Inhouse reusable tools: Verifast framework, Zebu accelerator platform
Execute ownership at Block, Section and SoC levels. Have implemented 600 Mn gate count designs, 600mm2 chips and up to 60 multi clock domains, timing closure in 120 different corners with maximum core frequency of 2.5 GHz, IP hardening with 80% placement utilization, Low power implementation up to 24 power domains.
Expertise across chip, interface, performance and functional aspects to detect complex functional / manufacturing defects. Our test factory model approach for silicon validation enables customers to save 40% to 50% of validation cost over 4 years.In-house reusable tools: Post Silicon Validation framework, Silicon Validation Labs, Silicon Qualification Labs
Provide end-to-end solution for reduced turnaround time (TAT) at improved quality levels with our in-depth knowledge and vast experience in handling complex ASIC / FPGA / SoC /Chiplet designs with our proven and well-established Analog, Digital and Mixed Signal design methodologies and processes. Our manufacturing partners can help us provide you a single point interface, if needed.