Overview
HCLTech’s Silicon Design Services group has extensive experience of working with top chip manufacturers, foundries, OEMs and Start-ups across globe for the last 25 years. The team of 1700+ VLSI engineers has well-proven capabilities in Analog, Digital and Mixed Signal designs to handle the challenges of ‘Concept to Chip’ and have successfully delivered 1000+ projects across different technology nodes.
We comprehend changing customer needs and accordingly develop and deliver innovative future-enabled solutions. We are well equipped to complement and support our customers in sustaining their current product portfolio by handling the derivative designs so that they can focus on futuristic product solutions. Our engineers have varying levels of hands-on experience in domain knowledge, latest technologies, design methodologies, modeling languages and verification techniques used in the industry.
Our Silicon Validation Labs, ATE Tester Labs, Qual Labs help our customer get not just a well-designed Silicon, but also a fully Qualified Silicon that can be manufactured seamlessly. Our foundry and OSAT partners help customers to get a full end to end turnkey Silicon solution.
HCLTech Will be at SEMICONDUCTOR360 LIVE 2021 and our experts will be available to meet you.
Click here to register for the event.
Our Key Differentiators
Speaking Session
Global Opportunities In The New Renaissance
Samir Patel, Chief Strategy Officer, Semiconductor Business, HCLTech
Date: 16th March, 2021 | 10:25 – 10:45 Israel Standard Time
After meteoric rise of semiconductor industry in 80s and 90s and being relatively stagnant from 2000-2010, we have seen a renaissance in our industry for last decade or so. It has truly become a global industry with most sophisticated manufacturing technologies and intricate design techniques. Its products were used mainly in a single computing appliance in high income families to all kinds of products for the entire humanity on earth. This has opened up many opportunities for enterprising folks but with new and different challenges in identifying and executing on the opportunities. This talk will explore the required context setting as well as some of the trends that can be used as a guide for each one of us to forge their unique paths to achieve success and take our industry to new heights in the near future.
Agile IP Development: Reusable Analog Building Blocks Across IPs
Siddharth Katare, Chief Architect, Analog Design Group, HCLTech
Date: 16th March, 2021 | 13:40 – 14:00 Israel Standard Time
ASIC developers often struggle to acquire off-the-shelf analog mixed signal (AMS) IP. The primary reason is not the scarcity of AMS IPs but because “one-size-fit-all” does not work, and performance is very susceptible to variation in ASIC requirements. The process technology node including various flavors of the same process, area, power, noise, package are a few such variables which makes it hard to build reusable AMS IPs. The benefit to ASIC developers in having reusable IPs will be tremendous since it would reduce time and cost significantly. Building flexible AMS IPs that can be reused, often results in increased power or increased area, neither of which can be tolerated. By breaking the AMS IPs into blocks we show how to provide agility in analog reuse methodology. Breaking the analog IPs further into Macros enables better reuse across various IPs. The Macros are configurable micro building blocks which are put together to build the analog portion of an AMS IP. By applying appropriate constraints on devices, area, power and performance we can create a library of Macros which provides a huge benefit in cost savings and time to market, without incurring power or area penalties.